Refer to FIG. 1, which is a schematic circuit diagram of a conventional dual-port (i.e., 2-port) static random access memory (SRAM) unit. It is different from the single port static random access memory in that in addition to the latch unit 10 composed of four transistors, and a first switch set 11, the dual-port static random access memory further comprises a second switch set 12 which allows a peripheral reading/writing circuit (not shown) coupled to the memory to perform data reading from or data writing into the latch unit 10 and other latch unit in the same row (not shown) at the same time via a first port word line WLA and a second port word line WLB, respectively.
In order to provide a margin necessary for reading data from or writing data into different latch units in the same row at the same time, the conventional reading/writing circuit has to provide a large enough word line pulse width, and keep the selected word line at a high voltage level for a duration long enough to ensure that the data reading and writing can be done correctly even if the worst case occurs. However, this would result in the following drawbacks: firstly, too much power would be consumed; and, secondly, the long turn-on time of the word lines would increase the risk of affecting correctness of the stored data due to environment noises.